The invention relates to a method for retiming one or several digital data signal(s) each consisting of a number of successive bits, wherein the data signal(s) is/are sampled by an internal clock signal generated from an external clock signal, and a circuit for retiming such digital data signal(s).
When transmitting rapid digital data signals in the form of a number of successive bits or a bit stream, e.g. from a laser driver to an optical transmission link, it is usually necessary to perform a so-called retiming of the data signal(s), wherein the individual bits are synchronised with a clock signal. At very high data rates, the individual bit periods are, naturally, very short; the bit period at 2.5 GHz is, e.g., only 400 ps. Hence, in every bit the digital data signal is stable only for a short period, and therefore it is important that the incoming data signal is sampled quite accurately in the centre of the bit period, or in the centre of the eye diagram as it is also termed. Since the temporal characteristic of the data signal as well as the clock signal is sensitive to e.g. process and temperature variations, it is difficult prior to the sampling to ensure that the synchronisation between them is sufficient for the sampling actually to be effected approximately in the centre of the bit period, or at least it places heavy demands on the mutual synchronisation between the clock signal and the digital data signal(s).
Therefore, it has so far been necessary in the preceding circuits to ensure that these requirements are met. However, usually this requires an adjustment of said circuit, and since this adjustment is to be performed separately for each individual circuit during production, it is a process that makes the product considerably more expensive and more complicated.
Thus, it is an object of the invention to set out a method of the above type, wherein there are no strict requirements as to the synchronisation between the data signal(s) and the clock signal, and wherein an individual adjustment of the synchronisation in the preceding circuits is thus avoided.
According to the invention this is achieved by a method of retiming one or several digital data signal(s) by a retiming circuit, each digital data signal comprising a number of successive bits, the method comprises the steps of:
providing an external clock signal to the retiming circuit,
providing a digital data signal of the one or several digital data signal(s) to the retiming circuit,
deriving an internal clock signal from the external clock signal, the internal clock signal being synchronous to the external clock signal,
detecting a phase difference between the digital data signal and the internal clock signal,
generating a control signal indicating the phase difference,
adjusting a phase of the internal clock signal with respect to a phase of the digital data signal based on the control signal, and
sampling the digital data signal(s) by the internal clock signal.
Hereby, the internal clock signal is phase locked to the digital data signal in such a way that the latter is sampled approximately in the centre of each bit of the number of successive bits. By generating the internal clock signal based on the external clock signal so that the internal clock signal is synchronous to the external clock signal, and at the same time phase locking the internal clock signal to the data signal, the internal clock signal will automatically adjust itself so that the data signal is sampled at the appropriate point in time, i.e. in the centre of the bit period. As a result, there are no longer requirements as to the phase position of the external clock signal in relation to the data signal.
According to an embodiment of the invention, the control signal may be produced as a measure of the phase difference between the digital data signal and the internal clock signal, and the phase lock may be performed by means of this control signal.
Furthermore, the internal clock signal may be produced by delaying the external clock signal, said delay being controlled by said control signal. Alternatively, the internal clock signal may be derived from the external clock signal by delaying the internal clock signal in dependence of the control signal. A relatively simple solution is thus obtained in that the desired effect can be achieved with just one component, i.e. a controllable delay unit. A prerequisite for this solution is, however, that the external clock signal already has the same frequency as the data signal, and any jitter in the clock signal will be transferred to the retimed data signal.
Alternatively, the internal clock signal may be frequency locked to the external clock signal by means of a frequency locked loop, wherein a controlled oscillator produces the internal clock signal controlled by a steering signal which is produced as a measure of a frequency variation between the internal and the external clock signals, and said control signal may be combined with said steering signal before the latter is provided to the oscillator. By using a frequency locked loop for generating the internal clock signal, the latter may be generated largely without jitter, causing the retimed data signal to be largely free of jitter, as well.
By low-pass filtering the steering signal with a first bandwidth before it is provided to the controlled oscillator, and low-pass filtering the control signal with a second bandwidth before it is combined with the steering signal, wherein said second bandwidth is narrower than said first bandwidth, the change of the control signal will be substantially slower than that of the frequency locked loop itself. Thus, one may ensure that the internal clock signal is in the correct phase position with respect to the data signal without affecting the desired frequency locking to the external clock signal.
Another alternative is to phase lock the internal clock signal to the external clock signal by means of a phase locked loop comprising a phase frequency detector (PFD), a first low pass filter with a first bandwidth and a controlled oscillator, such as a voltage controlled oscillator, similar to the frequency locked loop mentioned above. By generating the internal clock signal using a phase locked loop, the internal clock signal may be generated largely without jitter, causing the retimed data signal to be largely free of jitter, as well.
The frequency of at least one of the internal clock signal and the external clock signal, respectively, may be divided down prior to the production of the steering signal. Dividing down the internal clock signal when it is generated by means of a frequency locked loop allows the frequency lock operation to be performed at a frequency lower than that of the internal clock signal. Dividing down the external clock signal allows this signal as well to have a frequency higher than that at which the frequency lock operation is performed. Thus, performing one (or both) of these divisions also allows the frequency of the internal clock signal to differ from the frequency of the external clock signal.
As mentioned, the invention further relates to a circuit for retiming one or several digital data signal(s) each consisting of a number of successive bits, the circuit being designed to generate an internal clock signal from an external clock signal, and for sampling the data signal by means of said internal clock signal. The retiming circuit comprises phase comparison means adapted to generate a control signal indicating a phase difference between a digital data signal of the one or several digital data signals and an internal clock signal, an internal clock unit adapted to derive the internal clock signal from the control signal and an external clock signal provided to the retiming circuit, the internal clock signal being synchronous to the external clock signal, data sampling means adapted to receive the one or several digital data signal(s) and to sample the digital data signal(s) by the internal clock signal, whereby a phase of the internal clock signal is adjusted with respect to a phase of the digital data signal(s) based on the control signal provided to the internal clock means.
The phase comparison means may comprise any means capable of providing a control signal based on the detected phase difference between the digital data signal of the one or several digital data signal(s) and the internal clock signal, the phase comparison means may comprise a phase detector, preferably a phase detector as shown in FIG. 2, or a phase frequency detector, etc,
The data sampling means may be any means adapted to receive the one or several digital data signal(s) and to sample the digital data signal(s) by the internal clock signal, the data sampling means may thus comprise one or more flip flop(s), a multiplexer, etc.
The fact that the circuit is designed to phase lock the internal clock signal to the data signal so that the latter is sampled approximately in the centre of every bit results in the internal clock signal being able to adjust itself automatically so that the data signal is sampled at the correct point in time, i.e. in the centre of the bit period. As a result, there are no longer requirements as to the phase position of the external clock signal in relation to the data signal.
In an appropriate embodiment of the invention, the circuit is designed to perform the phase lock of the internal clock signal to the data signal by means of a control signal expressing the phase difference between the data signal and the internal clock signal.
The circuit may comprise a controllable delay unit designed in such a way that said control signal may control it, and be designed to provide the internal clock signal by letting the external clock signal pass said delay unit. A relatively simple solution is thus obtained in that the desired effect can be achieved with just one component, i.e. a controllable delay unit. A prerequisite for this solution is, however, that the external clock signal already has the same frequency as the data signal, and any jitter in the clock signal will be transferred to the retimed data signal.
The retiming circuit may comprise a phase locked loop or a frequency locked loop adapted to receive and lock onto the external clock signal to provide the internal clock signal. The phase or frequency locked loops may comprise a first low-pass filter with a first bandwidth, and the phase or frequency locked loops may, further, comprise a second low-pass filter with a second bandwidth adapted to filter the control signal prior to being applied to a node of the phase or frequency locked loops. In a preferred embodiment the first bandwidth is larger, such as between 10 and 20 times larger, than the second bandwidth.
In one preferred embodiment, the circuit may, thus, comprise a phase locked loop or a frequency locked loop, by means of which the internal clock signal may be phase locked or frequency locked to the external clock signal, the phase or frequency locked loop comprising a phase frequency detector unit which is designed to produce a steering signal as a measure of a phase variation or a frequency variation between the internal and external clock signals and a controlled oscillator which is designed to produce the internal clock signal controlled by the steering signal, and further comprise means for combining said control signal with said steering signal before the latter is provided to the oscillator. By use of a phase locked loop or a frequency locked loop for generating the internal clock signal, the latter may be generated largely without jitter, causing the retimed data signal to be largely free of jitter, as well.
The circuit may comprise a first low-pass filter with a first bandwidth for filtering the steering signal before it is provided to the controlled oscillator, as well as a second low-pass filter with a second bandwidth for filtering the control signal before it is combined with the steering signal, wherein said second bandwidth is narrower than said first bandwidth, whereby the control signal changes substantially slower than the frequency locked loop itself. Thus, one may ensure that the internal clock signal is in the correct phase position in relation to the data signal without affecting the desired phase or frequency lock to the external clock signal.
Furthermore, the circuit may comprise means for dividing down the frequency of at least one of the internal clock signal and the external clock signal, respectively, before they are provided to the oscillator. The circuit may for example comprise a first divider circuit arranged with a feed-back path of the phase locked loop or the frequency locked loop, the first divider circuit being adapted to divide a feed-back path loop signal by an integer ratio, K, whereby the frequency of the internal clock, signal which samples the digital data signal is multiplied by K with respect to the external clock.
Dividing down the internal clock signal when it is generated by means of a phase or frequency locked loop enables the phase lock or the frequency lock operation to be performed at a frequency lower than that of the internal clock signal. Dividing down the external clock signal allows this signal as well to have a frequency higher than that at which the phase or frequency lock operation is performed. Thus, the performance of one (or both) of these divisions also allows the frequency of the internal clock signal to differ from the frequency of the external clock signal.
In another preferred embodiment of the invention the one or several digital data signals may form part of a data bus carrying several associated digital data signals. The data sampling means may comprise one or several D-FFs being adapted to receive the internal clock signal to sample a respective digital data signal of the one or several digital data signal(s).
The retiming circuit may further comprise a multiplexer adapted to receive the several associated digital data signals and to generate an outgoing serial digital data signal from the several associated digital data signals, the multiplexer being clocked by a clock signal derived from the internal clock signal.